A Single Integrated Solution for Next-Generation RFIC, RF Module, and Multi-Chip Module Design
Kristin Fullerton, Senior Application Engineer Architect

Cadence

A Single Integrated Solution for Next-Generation RFIC, RF Module, and Multi-Chip Module Design

In recent years the amount of RF content in IC designs has grown substantially and as these designs become more complex, analysis can no longer be done in isolation. The design does not end at the boundary of the RFIC; the engineer needs to make sure that the IC works in the context of the module and the substrate. Along with the increasing complexity, the new era of More than Moore means that analysis and verification requirements will extend to more complex structures such as heterogeneous integration of chiplets.

Cadence is responding to these challenges with the Virtuoso® RF Solution, which provides a single, integrated design flow that combines the industry-leading Virtuoso platform with best-in-class tools for packaging and analysis. This presentation will overview the Virtuoso RF solution, highlighting its benefits to the IC and package designer and where it fits in the overall Cadence product portfolio.

 

Kristin Fullerton is a senior application engineer architect at Cadence supporting the Virtuoso RF Solution product line. Prior to Cadence, she held positions as an application engineer at Synopsys and an analog design engineer at Harris Semiconductor. Kristin holds a BSEE and an MSEE from the University of Florida.